Such a video-processing system and data display system are known from European patent application EP-A 840522. This patent application describes a video-processing unit which is used in video display systems based on spatial light modulators such as a liquid crystal display or a digital micro-mirrored device (DMD). These spatial light modulators comprise a number of pixels arranged in a rectangular matrix. This matrix comprises a number of rows and columns. Each row comprises an equal number of the pixels. In general, the number of rows does not match with a number of rows of the input data signal to be displayed, or the aspect ratio of the image represented by the input data signal does not match with the aspect ratio of the spatial light modulator. Therefore, the processing means resizes the input data in such a way that the number of rows of the resized output data matches the number of rows of the matrix, or the aspect ratio of the image of the resized data output signal matches the aspect ratio of the matrix. The resizing operation requires some kind of filtering or interpolating. Therefore, information corresponding to more than one line of the image is required. The memory means is used for this information. In the known video-processing unit, the memory means precedes the processing means and the resized output data is coupled to a video output unit. Processed information is thus transferred to a subsequent process.
A disadvantage of the known video-processing unit is that a display-specific type of processing cannot be performed in this video-processing unit, for example a bit plane conversion in order to drive the single reflective LCD panel or the DMD panel or a keystone correction for geometric distortions.
It is, inter alia, an object of the invention to provide a video-processing unit with a flexible architecture which is capable of both handling resizing input data and other types of processing. To this end, a video-processing unit according to the invention is characterized in that an output of the processing means is coupled to an input of the memory manager, and in that the memory manager is further arranged to transfer the output data signal from the processing means to the memory means for storing the output data signal, and to transfer the stored output data signal from the memory means to the output device. Feedback of the output data signal to the memory manager enables the storage of the scaled data output signal in the memory. As a result, the stored scaled data output signal can be used as a further input signal for a second or further kind of operation by the processing means such as the display-specific processing of the resized data output signal. The available bandwidth for the memory means and the size of the memory means limits the number of possible processes in the video-processing unit. Furthermore, the feedback of the processing means to the memory manager enables the realization of two kinds of data-processing architectures. In a first architecture, the processing means is situated behind the memory means, for example a frame buffer, and in a second architecture, the processing means precedes the frame buffer. So, advantages of both processing architectures may be available. A first advantage in the case of the processing means being situated behind the frame buffer is that a horizontal interleaved sampling of an image is possible. This allows an A/D converter to run at half an actual clock frequency corresponding to the input data signal and may lead to the application of economic A/D converters. Further advantages are that an optimum scaling of interlaced still images is possible and that a minimum number of line memories is required.
A first advantage in the case of the processing means precedes the frame buffer is that the On-Screen-Display (OSD) image is not scaled. As a result, the size of the OSD image is independent of the resolution of the incoming video data. A further advantage is that, by sharing the memory and the processing means for different processes, an economic design of the video-processing to a single chip is possible.
A particular embodiment of the video-processing unit according to the invention is characterized in that the memory manager is further arranged to transfer the stored data output signal to the processing means, and said processing means is further arranged to execute a further operation on the stored data output signal. For example, a first process may be a resizing operation on the input data into the resize output data. A second process may be a display-specific operation on the resized output data into a display-specific output data.
A further embodiment of the video-processing unit according to the invention is characterized in that said processing means and said memory manager are arranged to execute different processes in time multiplex.
A further embodiment of the video-processing unit according to the invention is characterized in that said processing means, said memory manager and the memory are comprised on a single integrated circuit. A high degree of integration enables an economic design of the video display system.
A further embodiment of the video-processing unit according to the invention is characterized in that said processing means is arranged to resize an image represented by said input data signal.
A further embodiment of the video-processing unit according to the invention is characterized in that said processing means is further arranged to convert said input data signal representing an image into a color-sequential output signal. In order to reduce the size and weight of a video display system, only a single light-valve display device can be used in combination with a light source and color filter means, which alters the color of the light sequentially in, for example, red, green and blue. In that case, the information of the output signal supplied to the light-valve display device should contain serial red, green or blue information synchronously with the color of the color filter means. In general, most video data signals comprise the information of red, green and blue of a pixel in parallel. Conversion from the parallel color information into serial color information is then necessary and can be performed by a process running in the video-processing unit.
A further embodiment of the video-processing unit according to the invention is characterized in that said processing means is further arranged to convert said input data signal representing an image into a sub-field modulated output signal for controlling the output device. Sub-field modulation is known from the cited European patent application EP-A 840522. Some types of displays use a digital control of individual pixels, such as, for example the DMD. The pixels of the DMD can maintain their ‘on’ or ‘off’-state for controlled display. Pulse-width modulation techniques are used to achieve intermediate illumination between white and black levels. A further embodiment of the video-processing unit according to the invention is characterized in that the memory manager has a further input for a second input data signal, and the memory manager is further arranged to transfer the second data input signal to the memory means.
The invention further relates to a video display system. It is an object of the invention to provide a video display system with a flexible architecture which is capable of handling resizing input data as well as a display-specific type of processing. To this end, a video display system according to the invention is characterized in that the video display system comprises a digital video-processing unit as described hereinbefore, having the output for providing an output data signal and a display system coupled to the output of said digital video-processing unit for displaying the output data signal.